/**********************************************************************
	File: mpsoc.v 
	
	Copyright (C) 2013  Alireza Monemi

    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
	
	
	Purpose:
	 Generating a mesh based multiprocessor system on (MPSOC) based on
	 NIOS II Altera processor. The code tested on the Altera DE2-115 
	 educational. U can connect the external SDRAM to one of the NoC
	 routers by enablaing it as input parameter. 
	 
	Info: monemi@fkegraduate.utm.my
********************************************************************/	
	
	
	
/*	
	
	
	// the routers address in mesh topology
	CORE_NUM
	(x,y)
	
	0						  	1									X_NODE_NUM-1
	(0		,	0)			 	(1		,		0)	....			(X_NODE_NUM-1,		0)
	
	X_NODE_NUM		  		X_NODE_NUM+1					2*X_NODE_NUM-1
	(0		,	1)				(1		,		1)	....			(X_NODE_NUM-1,		1)
		.
		.
	(Y_NODE_NUM-1)*X_NODE_NUM								Y_NODE_NUM*X_NODE_NUM-1
	(0,Y_NODE_NUM)			(1,Y_NODE_NUM)	.....			(X_NODE_NUM-1,Y_NODE_NUM-1)


//routers port interconnection  


in[CORE_NUM][port_num]


in	[x,y][1] <------	 	out [x+1		,y	 ][3]	;
in	[x,y][2] <------		out [x		,y-1][4] ;
in	[x,y][3] <------		out [x-1		,y	 ][1]	;
in	[x,y][4] <------		out [x		,y+1][2]	;
	
port num
local = 0
east  = 1
north = 2
west  = 3
south = 4


****************************/

`include "define.v"


module mpsoc #(
	parameter VC_NUM_PER_PORT 			=	`VC_NUM_PER_PORT_DEF ,
	parameter PYLD_WIDTH 				=	`PYLD_WIDTH_DEF,
	parameter BUFFER_NUM_PER_VC		=	`BUFFER_NUM_PER_VC_DEF,
	
	parameter X_NODE_NUM					=	`X_NODE_NUM_DEF,
	parameter Y_NODE_NUM					=	`Y_NODE_NUM_DEF,
	parameter NIOS_RAM_WIDTH			=	13,
	parameter S_ADDR_SIZE				=	2,
	parameter SW_OUTPUT_REGISTERED	=	0,// 1: registered , 0 not registered
	parameter CMD_RAM_ADDR_WIDTH		=	5,
	parameter COD_RAM_ADDR_WIDTH		=	8,
	
	parameter SDRAM_EN					=	1,//  0 : disabled  1: enabled 
	parameter SDRAM_SW_X_ADDR			=	0,
	parameter SDRAM_SW_Y_ADDR			=	1,
	parameter SDRAM_NIC_CONNECT_PORT	=	0, 
	parameter SDRAM_ADDR_WIDTH			=	25,
	parameter CAND_VC_SEL_MODE			=	0,
	
	parameter JTAG_INTERFACE_EN		=	1, // if disabled the jtag can just send packet but can not recieve any packet
	parameter JTAG_SW_X_ADDR			=	0,
	parameter JTAG_SW_Y_ADDR			=	0,
	parameter JTAG_NIC_CONNECT_PORT	=	0,
	
	parameter PORT_NUM					=	5,
	parameter FLIT_TYPE_WIDTH			=	2,
	parameter VC_FULL_WIDTH				=  VC_NUM_PER_PORT*2,
	parameter PORT_SEL_WIDTH			=	PORT_NUM-1,//assum that no port whants to send a packet to itself!
	parameter VC_ID_WIDTH				=	VC_NUM_PER_PORT,
	parameter FLIT_WIDTH					=	PYLD_WIDTH+ FLIT_TYPE_WIDTH+VC_ID_WIDTH,
	parameter FLIT_ARRAY_WIDTH			=	FLIT_WIDTH		*	PORT_NUM,
	parameter CREDIT_ARRAY_WIDTH		=	VC_NUM_PER_PORT	*	PORT_NUM,
	parameter TOTAL_ROUTERS_NUM		=	X_NODE_NUM		* Y_NODE_NUM,
	parameter M_ADDR_SIZE				=	NIOS_RAM_WIDTH+2,
	
	parameter NIC_S_ADDR_ARRAY_WIDTH =	S_ADDR_SIZE*TOTAL_ROUTERS_NUM,
	parameter NIC_S_DATA_ARRAY_WIDTH	=	32 * TOTAL_ROUTERS_NUM,
	parameter RAM_ARRAY_ADDR_WIDTH	=	M_ADDR_SIZE*TOTAL_ROUTERS_NUM
	
)(
	//synthesis translate_off
	input		[TOTAL_ROUTERS_NUM-1			:0]		nic_s_chipselect,
	input 	[TOTAL_ROUTERS_NUM-1			:0]   	nic_s_write,
	input		[TOTAL_ROUTERS_NUM-1			:0]   	nic_s_read,
	output	[TOTAL_ROUTERS_NUM-1			:0]		nic_s_waitrequest,
	input		[NIC_S_ADDR_ARRAY_WIDTH-1	:0]		nic_s_address_array,  
	input		[NIC_S_DATA_ARRAY_WIDTH-1	:0]		nic_s_writedata_array,
	output	[NIC_S_DATA_ARRAY_WIDTH-1	:0] 		nic_s_readdata_array,
	
	input 	[TOTAL_ROUTERS_NUM-1			:0]		ram_we,
	input		[RAM_ARRAY_ADDR_WIDTH-1		:0]		ram_addr_array,
	input		[NIC_S_DATA_ARRAY_WIDTH-1	:0]		ram_data_array,
	

	input		[31								:0]		cmd_data,
	input		[CMD_RAM_ADDR_WIDTH-1		:0]		cmd_addr,
	input														cmd_we,
	output	[31								:0]		cmd_q_b,
	
	input		[31								:0]		code_data,
	input 	[COD_RAM_ADDR_WIDTH-1		:0]		code_addr,
	input														code_we,
	output													code_q_b,
	
	//synthesis translate_on
	
	
	
	input														reset,
	output													nios_reset,
	input 													clk,
	output	[TOTAL_ROUTERS_NUM-1			:0]		led,
	output													jtag_led,
	
	output  [12									:0] 		sdram_addr,        // sdram_wire.addr
	output  [1									:0]  		sdram_ba,          //           .ba
	output         										sdram_cas_n,       //           .cas_n
	output         										sdram_cke,         //           .cke
	output         										sdram_cs_n,        //           .cs_n
	inout   [31									:0]		sdram_dq,          //           .dq
	output  [3									:0] 		sdram_dqm,         //           .dqm
	output         										sdram_ras_n,       //           .ras_n
	output         										sdram_we_n,        //           .we_n
	output         										sdram_clk		    //  sdram_clk.clk
	);
	
	


			
wire [FLIT_ARRAY_WIDTH-1		:	0] router_flit_in_array 	[TOTAL_ROUTERS_NUM-1			:0];
wire [PORT_NUM-1					:	0] router_wr_in_en_array	[TOTAL_ROUTERS_NUM-1			:0];	
wire [CREDIT_ARRAY_WIDTH-1		:	0] router_credit_out_array	[TOTAL_ROUTERS_NUM-1			:0];
wire [PORT_NUM-1					:	0]	router_wr_out_en_array	[TOTAL_ROUTERS_NUM-1			:0];
wire [FLIT_ARRAY_WIDTH-1		:	0] router_flit_out_array 	[TOTAL_ROUTERS_NUM-1			:0];
wire [VC_FULL_WIDTH	-1			:	0]	router_nic_vc_full		[TOTAL_ROUTERS_NUM-1			:0];
wire [CREDIT_ARRAY_WIDTH-1		:	0]	router_credit_in_array	[TOTAL_ROUTERS_NUM-1			:0];


wire [FLIT_WIDTH-1				:	0]	nic_flit_out				[TOTAL_ROUTERS_NUM-1			:0];   
wire [TOTAL_ROUTERS_NUM-1		:	0]	nic_flit_out_wr; 
wire [VC_NUM_PER_PORT-1			:	0]	nic_credit_in 				[TOTAL_ROUTERS_NUM-1			:0];
wire [FLIT_WIDTH-1				:	0]	nic_flit_in 				[TOTAL_ROUTERS_NUM-1			:0];   
wire [TOTAL_ROUTERS_NUM-1		:	0]	nic_flit_in_wr;  
wire [VC_NUM_PER_PORT-1			:	0]	nic_credit_out 			[TOTAL_ROUTERS_NUM-1			:0];					

wire [FLIT_WIDTH-1				:	0]	jtag_flit_out;	
wire											jtag_flit_out_wr;
wire [VC_NUM_PER_PORT-1			:	0] jtag_credit_in;

//avalon slave interface signals


wire 	[S_ADDR_SIZE-1				:0]	nic_s_address				[TOTAL_ROUTERS_NUM-1			:0];   
wire 	[31							:0]	nic_s_writedata			[TOTAL_ROUTERS_NUM-1			:0];    
wire	[31							:0] 	nic_s_readdata				[TOTAL_ROUTERS_NUM-1			:0];   


wire   [ 31							: 0]	ram_data						[TOTAL_ROUTERS_NUM-1			:0]; 
wire   [M_ADDR_SIZE-1			: 0]	ram_addr						[TOTAL_ROUTERS_NUM-1			:0]; 



	
	

  
 
genvar x,y;
generate 

	for	(x=0;	x<X_NODE_NUM; x=x+1) begin :x_loop
		for	(y=0;	y<Y_NODE_NUM;	y=y+1) begin: y_loop

		if( SDRAM_EN	==	1 && x == SDRAM_SW_X_ADDR	&& y ==  SDRAM_SW_Y_ADDR) begin : sdram_gen
		
			sdram_core #(
				.VC_NUM_PER_PORT			(VC_NUM_PER_PORT),
				.PYLD_WIDTH 				(PYLD_WIDTH),
				.BUFFER_NUM_PER_VC		(BUFFER_NUM_PER_VC),
				.FLIT_TYPE_WIDTH			(FLIT_TYPE_WIDTH),
				.PORT_NUM					(PORT_NUM),
				.X_NODE_NUM					(X_NODE_NUM),
				.Y_NODE_NUM					(Y_NODE_NUM),
				.SW_X_ADDR					(SDRAM_SW_X_ADDR),
				.SW_Y_ADDR					(SDRAM_SW_Y_ADDR),
				.NIC_CONNECT_PORT			(SDRAM_NIC_CONNECT_PORT),
				.SDRAM_ADDR_WIDTH			(SDRAM_ADDR_WIDTH),
				.CAND_VC_SEL_MODE			(CAND_VC_SEL_MODE)
			)
			the_sdram
			(
				.reset						(reset) ,	
				.clk							(clk) ,
				
				// NOC interfaces
				.flit_out					(nic_flit_out				[`CORE_NUM(x,y)]),	
				.flit_out_wr				(nic_flit_out_wr			[`CORE_NUM(x,y)]),	
				.credit_in					(nic_credit_in				[`CORE_NUM(x,y)]), 
				
				.flit_in						(nic_flit_in				[`CORE_NUM(x,y)]),	
				.flit_in_wr					(nic_flit_in_wr			[`CORE_NUM(x,y)]),	
				.credit_out					(nic_credit_out			[`CORE_NUM(x,y)]) ,
				
				.sdram_addr					(sdram_addr) ,	
				.sdram_ba					(sdram_ba) ,	
				.sdram_cas_n				(sdram_cas_n) ,	
				.sdram_cke					(sdram_cke) ,	
				.sdram_cs_n					(sdram_cs_n) ,	
				.sdram_dq					(sdram_dq) ,	
				.sdram_dqm					(sdram_dqm) ,	
				.sdram_ras_n				(sdram_ras_n) ,	
				.sdram_we_n					(sdram_we_n) ,	
				.sdram_clk					(sdram_clk) 	
			);
		
		
	end else if ( JTAG_INTERFACE_EN	==	1 && x == JTAG_SW_X_ADDR	&& y ==  JTAG_SW_Y_ADDR) begin : jtag_gen
		
		
		jtag_interface #(
		.VC_NUM_PER_PORT 		(VC_NUM_PER_PORT),
		.PYLD_WIDTH 			(PYLD_WIDTH ),
		.BUFFER_NUM_PER_VC	(BUFFER_NUM_PER_VC),	
		.FLIT_TYPE_WIDTH		(FLIT_TYPE_WIDTH),
		.PORT_NUM				(PORT_NUM),
		.X_NODE_NUM				(X_NODE_NUM),
		.Y_NODE_NUM				(Y_NODE_NUM),
		.SW_X_ADDR				(JTAG_SW_X_ADDR),
		.SW_Y_ADDR				(JTAG_SW_Y_ADDR),
		.NIC_CONNECT_PORT		(JTAG_NIC_CONNECT_PORT	),	 // 0:Local  1:East, 2:North, 3:West, 4:South 
		.NIOS_RAM_WIDTH		(NIOS_RAM_WIDTH),
		.CMD_RAM_ADDR_WIDTH	(CMD_RAM_ADDR_WIDTH),
		.COD_RAM_ADDR_WIDTH	(COD_RAM_ADDR_WIDTH)
	)
	jtag_interface_inst
	(
		.clk							(clk) ,	
		.reset						(reset) ,	
		//synthesis translate_off
		.cmd_data					(cmd_data),
		.cmd_addr					(cmd_addr),
		.cmd_we						(cmd_we),
		.cmd_q_b						(cmd_q_b),
		
		.code_data					(code_data),
		.code_addr					(code_addr),
		.code_we						(code_we),
		.code_q_b					(code_q_b),
		
		//synthesis translate_on
		 
		.nios_reset					(nios_reset) ,	
		.led							(jtag_led) ,	
		
		//noc interface 
		.flit_out					(nic_flit_out				[`CORE_NUM(x,y)]),	
		.flit_out_wr				(nic_flit_out_wr			[`CORE_NUM(x,y)]),	
		.credit_in					(nic_credit_in				[`CORE_NUM(x,y)]), 
			
		.flit_in						(nic_flit_in				[`CORE_NUM(x,y)]),	
		.flit_in_wr					(nic_flit_in_wr			[`CORE_NUM(x,y)]),	
		.credit_out					(nic_credit_out			[`CORE_NUM(x,y)]) 
	);	
		
		
		
		
		end else begin : cpu_core_gen 
			 cpu_core #(
				.VC_NUM_PER_PORT			(VC_NUM_PER_PORT),
				.PYLD_WIDTH 				(PYLD_WIDTH),
				.BUFFER_NUM_PER_VC		(BUFFER_NUM_PER_VC),
				.FLIT_TYPE_WIDTH			(FLIT_TYPE_WIDTH),
				.PORT_NUM					(PORT_NUM),
				.X_NODE_NUM					(X_NODE_NUM),
				.Y_NODE_NUM					(Y_NODE_NUM),
				.SW_X_ADDR					(x),
				.SW_Y_ADDR					(y),
				.NIC_CONNECT_PORT			(0),		// 0:Local  1:East, 2:North, 3:West, 4:South 
				.NIOS_RAM_WIDTH			(NIOS_RAM_WIDTH),
				.S_ADDR_SIZE				(S_ADDR_SIZE)
			)
			ip_core
			(
				.reset						(reset) ,	
				.nios_reset					(nios_reset) ,	
				.clk							(clk) ,
				// synthesis translate_off
		
				.s_chipselect				(nic_s_chipselect			[`CORE_NUM(x,y)]),
				.s_write						(nic_s_write				[`CORE_NUM(x,y)]),
				.s_read						(nic_s_read					[`CORE_NUM(x,y)]),
				.s_address					(nic_s_address				[`CORE_NUM(x,y)]),
				.s_writedata				(nic_s_writedata			[`CORE_NUM(x,y)]), 
				.s_readdata					(nic_s_readdata			[`CORE_NUM(x,y)]),
				.s_waitrequest				(nic_s_waitrequest		[`CORE_NUM(x,y)]),
		
				.ram_data					(ram_data					[`CORE_NUM(x,y)]),
				.ram_addr					(ram_addr					[`CORE_NUM(x,y)]),
				.ram_we						(ram_we						[`CORE_NUM(x,y)]),
				// synthesis translate_on
		
				.led							(led							[`CORE_NUM(x,y)]),	
				.flit_out					(nic_flit_out				[`CORE_NUM(x,y)]),	
				.flit_out_wr				(nic_flit_out_wr			[`CORE_NUM(x,y)]),	
				.credit_in					(nic_credit_in				[`CORE_NUM(x,y)]), 
				//.flit_out_vc_full		(nic_flit_out_vc_full	[`CORE_NUM(x,y)]),	
				.flit_in						(nic_flit_in				[`CORE_NUM(x,y)]),	
				.flit_in_wr					(nic_flit_in_wr			[`CORE_NUM(x,y)]),	
				.credit_out					(nic_credit_out			[`CORE_NUM(x,y)]) 
			); 
		end
	
		router#(
				.VC_NUM_PER_PORT			(VC_NUM_PER_PORT),
				.BUFFER_NUM_PER_VC		(BUFFER_NUM_PER_VC),
				.PORT_NUM					(PORT_NUM),
				.PYLD_WIDTH 				(PYLD_WIDTH),
				.FLIT_TYPE_WIDTH			(FLIT_TYPE_WIDTH),
				.X_NODE_NUM					(X_NODE_NUM),
				.Y_NODE_NUM					(Y_NODE_NUM	),
				.SW_X_ADDR					(x),
				.SW_Y_ADDR					(y),
				.SW_OUTPUT_REGISTERED	(SW_OUTPUT_REGISTERED)
				
		
		)
		the_router
		(
			.wr_in_en_array				(router_wr_in_en_array		[`CORE_NUM(x,y)]),
			.flit_in_array					(router_flit_in_array		[`CORE_NUM(x,y)]),
			.credit_out_array				(router_credit_out_array	[`CORE_NUM(x,y)]),
			.wr_out_en_array				(router_wr_out_en_array		[`CORE_NUM(x,y)]),
			.flit_out_array				(router_flit_out_array		[`CORE_NUM(x,y)]),
			.credit_in_array				(router_credit_in_array		[`CORE_NUM(x,y)]),
			.clk								(clk),
			.reset							(reset)
		);

//routers pin assignment

		
//in	[x,y][1] = 	out [x+1		,y	 ][3]	;
//in	[x,y][2] =	out [x		,y-1][4] ;
//in	[x,y][3] =	out [x-1		,y	 ][1]	;
//in	[x,y][4] =	out [x		,y+1][2]	;

	
	//connection to the naibour nodes	
	if(x	<	X_NODE_NUM-1) begin
		assign	router_flit_in_array 	[`SELECT_WIRE(x,y,1,FLIT_WIDTH)] 		= router_flit_out_array 	[`SELECT_WIRE((x+1),y,3,FLIT_WIDTH)];
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)]	= router_credit_out_array	[`SELECT_WIRE((x+1),y,3,VC_NUM_PER_PORT)];
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][1]							= router_wr_out_en_array	[`CORE_NUM((x+1),y)][3];
	end else begin
		assign	router_flit_in_array 	[`SELECT_WIRE(x,y,1,FLIT_WIDTH)] 		=	{FLIT_WIDTH{1'b0}};
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,1,VC_NUM_PER_PORT)]	=	{VC_NUM_PER_PORT{1'b0}};
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][1]							=	1'b0;
	end 
		
	
	if(y>0) begin
		assign	router_flit_in_array 	[`SELECT_WIRE(x,y,2,FLIT_WIDTH)]			=	router_flit_out_array 	[`SELECT_WIRE(x,(y-1),4,FLIT_WIDTH)];
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)]	=  router_credit_out_array	[`SELECT_WIRE(x,(y-1),4,VC_NUM_PER_PORT)];
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][2]							=	router_wr_out_en_array	[`CORE_NUM(x,(y-1))][4];
	end else begin 
		assign 	router_flit_in_array 	[`SELECT_WIRE(x,y,2,FLIT_WIDTH)]			=	{FLIT_WIDTH{1'b0}};
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,2,VC_NUM_PER_PORT)]	=	{VC_NUM_PER_PORT{1'b0}};
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][2]							=	1'b0;
	end
	
	
	if(x>0)begin
		assign	router_flit_in_array 	[`SELECT_WIRE(x,y,3,FLIT_WIDTH)]			=	router_flit_out_array 	[`SELECT_WIRE((x-1),y,1,FLIT_WIDTH)] ;
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)]	=  router_credit_out_array	[`SELECT_WIRE((x-1),y,1,VC_NUM_PER_PORT)] ;
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][3]							=	router_wr_out_en_array	[`CORE_NUM((x-1),y)][1];
	end else	begin
		if(y==0 && JTAG_INTERFACE_EN == 0) begin 
		
		
			jtag_interface #(
				.VC_NUM_PER_PORT 		(VC_NUM_PER_PORT),
				.PYLD_WIDTH 			(PYLD_WIDTH ),
				.BUFFER_NUM_PER_VC	(BUFFER_NUM_PER_VC),	
				.FLIT_TYPE_WIDTH		(FLIT_TYPE_WIDTH),
				.PORT_NUM				(PORT_NUM),
				.X_NODE_NUM				(X_NODE_NUM),
				.Y_NODE_NUM				(Y_NODE_NUM),
				.SW_X_ADDR				(0),
				.SW_Y_ADDR				(0),
				.NIC_CONNECT_PORT		(3	),	 // 0:Local  1:East, 2:North, 3:West, 4:South 
				.NIOS_RAM_WIDTH		(NIOS_RAM_WIDTH),
				.CMD_RAM_ADDR_WIDTH	(CMD_RAM_ADDR_WIDTH),
				.COD_RAM_ADDR_WIDTH	(COD_RAM_ADDR_WIDTH)
			)
			jtag_interface_inst
			(
				.clk					(clk) ,	
				.reset				(reset) ,	
				//synthesis translate_off
				.cmd_data			(cmd_data),
				.cmd_addr			(cmd_addr),
				.cmd_we				(cmd_we),
				.cmd_q_b				(cmd_q_b),
				//synthesis translate_on
				 
				.nios_reset			(nios_reset) ,	
				.led					(jtag_led) ,	
				
				//noc interface 
				.flit_out			(jtag_flit_out) ,	
				.flit_out_wr		(jtag_flit_out_wr) ,	
				.credit_in			(jtag_credit_in),
				
				.flit_in				(),	
				.flit_in_wr			(),	
				.credit_out			()
				
				
				
			
			);	
		
		
			assign	router_flit_in_array 	[`SELECT_WIRE(x,y,3,FLIT_WIDTH)]			=  jtag_flit_out;
			assign	jtag_credit_in																	=	router_credit_out_array	[`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)];
			assign	router_wr_in_en_array	[`CORE_NUM(x,y)][3]							=	jtag_flit_out_wr;
		
		end
		else begin
			assign	router_flit_in_array 	[`SELECT_WIRE(x,y,3,FLIT_WIDTH)]			=  {FLIT_WIDTH{1'b0}};
			assign	router_credit_in_array	[`SELECT_WIRE(x,y,3,VC_NUM_PER_PORT)]	=	{VC_NUM_PER_PORT{1'b0}};
			assign	router_wr_in_en_array	[`CORE_NUM(x,y)][3]							=	1'b0;
		end //else
	end	
	
	if(y	<	Y_NODE_NUM-1)begin
		assign	router_flit_in_array 	[`SELECT_WIRE(x,y,4,FLIT_WIDTH)]			=	router_flit_out_array 	[`SELECT_WIRE(x,(y+1),2,FLIT_WIDTH)];
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)]	= 	router_credit_out_array	[`SELECT_WIRE(x,(y+1),2,VC_NUM_PER_PORT)];
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][4]							=	router_wr_out_en_array	[`CORE_NUM(x,(y+1))][2];
	end else 	begin
		assign	router_flit_in_array 	[`SELECT_WIRE(x,y,4,FLIT_WIDTH)]			=  {FLIT_WIDTH{1'b0}};
		assign	router_credit_in_array	[`SELECT_WIRE(x,y,4,VC_NUM_PER_PORT)]	=	{VC_NUM_PER_PORT{1'b0}};
		assign	router_wr_in_en_array	[`CORE_NUM(x,y)][4]							=	1'b0;
	end	
	
	//connection to the ip_core
	assign		router_flit_in_array 	[`SELECT_WIRE(x,y,0,FLIT_WIDTH)]			=	nic_flit_out		[`CORE_NUM(x,y)];
	assign		router_credit_in_array	[`SELECT_WIRE(x,y,0,VC_NUM_PER_PORT)]	=	nic_credit_out		[`CORE_NUM(x,y)];
	assign		router_wr_in_en_array	[`CORE_NUM(x,y)][0]							=	nic_flit_out_wr	[`CORE_NUM(x,y)];
		
	
	assign		nic_flit_in				[`CORE_NUM(x,y)] = router_flit_out_array 	[`SELECT_WIRE(x,y,0,FLIT_WIDTH)];
	assign		nic_flit_in_wr 		[`CORE_NUM(x,y)] = router_wr_out_en_array	[`CORE_NUM(x,y)][0];
	assign		nic_credit_in			[`CORE_NUM(x,y)] = router_credit_out_array[`SELECT_WIRE(x,y,0,VC_NUM_PER_PORT)];
	//assign		nic_flit_out_vc_full [`CORE_NUM(x,y)] = router_nic_vc_full	  [`CORE_NUM(x,y)];





//synthesis translate_off
	assign nic_s_address 	[`CORE_NUM(x,y)]		=	nic_s_address_array 	[(`CORE_NUM(x,y)+1)*S_ADDR_SIZE-1			: `CORE_NUM(x,y)*S_ADDR_SIZE	];
	assign nic_s_writedata	[`CORE_NUM(x,y)]		=  nic_s_writedata_array[(`CORE_NUM(x,y)+1)*32-1			: `CORE_NUM(x,y)*32	];
	assign nic_s_readdata_array	[(`CORE_NUM(x,y)+1)*32-1	: `CORE_NUM(x,y)*32] =nic_s_readdata	[`CORE_NUM(x,y)];
	assign ram_data			[`CORE_NUM(x,y)]		=	ram_data_array	[(`CORE_NUM(x,y)+1)*32-1			: `CORE_NUM(x,y)*32	];
	assign ram_addr			[`CORE_NUM(x,y)]		=	ram_addr_array 	[(`CORE_NUM(x,y)+1)*M_ADDR_SIZE-1			: `CORE_NUM(x,y)*M_ADDR_SIZE	];
//synthesis	translate_on	


	end //y
	end //x
endgenerate




endmodule
